In the prior art, there exists a major problem in the design of self-organizing fault tolerant systems which are utilized in digital processor systems. The problem involves the difficulty in making the system organize itself reliably in the presence of one or more hidden faults within any one or more digital processor in the system. When these hidden faults are present, they create a major problem in the reliability of the system since they are not disclosed by self-diagnosis procedures in each digital processor of the system. These faults may be hidden because they are intermittent, or because the self-diagnosis procedures do not cover them. Such faults may disrupt the process of self-reorganization and the resulting system operations thereafter.
The task of reducing or eliminating hidden faults in self-organizing computer or digital processor systems is alleviated, to some degree, by the following U.S. Pat. Nos.:
4,443,849 issued to Hiroyuki Ohwada on Apr. 17, 1984;
4,453,210 issued to Suzuki et al on June 5, 1984; and
4,321,666 issued to Tasar et al on Mar. 23, 1982.
In a modern LSI or VLSI environment, the problem of hidden faults in a self-organizing digital processor system may become acute. Each digital processor may consist of only a few integrated circuits, or even only one. With present technology, such integrated circuits have either a read-only-memory, or a volatile read-write memory. Thus each digital processor loses any and all alterable information in the event of a loss of power. A system of such digital processors often has to operate without manual intervention during key portions of its life cycle. Examples of such systems are spaceborne systems throughout their life or real-time military systems, or even real-time commercial systems, such as nuclear reactor control systems, to take an extremely critical example.